In fabrication and application of IC chips, with continuous improvement of very-large-scale integration (VLSI) process technology, current complementary metal-oxide-semiconductor (CMOS) IC fabrication technology has entered deep sub-micron stage. Size of metal-oxide-semiconductor (MOS) devices shrinks continuously. Thickness of gate oxide layer is continuously reduced. Voltage tolerance of MOS devices is significantly decreased. The harm of electrostatic discharge (ESD) to IC has become more and more significant. Therefore, ESD protection for IC becomes particularly important.
In order to improve ESD protection, input and output interface terminal (I/O pad) of a chip is often connected to an ESD protection circuit. The ESD protection circuit is configured to provide the internal circuit of the chip with a discharge path for ESD current, in order to prevent ESD from breaking down the internal circuit.
Silicon-controlled rectifier (SCR), also referred to as thyristor, is often used in ESD protection device. Under a normal condition, there is no conduction between the cathode and the anode of a thyristor. A positive trigger pulse needs to be applied to a control electrode to turn on the conduction between the cathode and the anode of the thyristor. Once the conduction of the thyristor is turned on and a stable current is formed, even if the externally voltage applied to the control electrode is removed, the conduction of the thyristor can remain on, until the current between the cathode and the anode is smaller than a minimum current for maintaining the conduction (i.e., a holding current) when the thyristor is turned off by itself.
FIG. 1 depicts a schematic circuit diagram of a conventional ESD protection circuit. As shown in FIG. 1, a to-be-protected device 4 releases its electrostatic charge via an electrostatic-discharging terminal 3. A first thyristor 1 and a second thyristor 2 can respectively use a bidirectional thyristor having the same specification. The first thyristor 1 has an anode connected to a high-voltage source line Vdd, and a cathode connected to the electrostatic-discharging terminal 3. The second thyristor 2 has an anode connected to the electrostatic-discharging terminal 3, and a cathode connected to a low-voltage source line Vss. Thus, regardless of the electric potential of the electrostatic-discharging terminal 3, electrostatic charge can be released toward the high-voltage source line Vdd or the low-voltage source line Vss via the first thyristor 1 and the second thyristor 2.
The anode and the cathode of the first thyristor 1 and the second thyristor 2 merely represent the input and output electrodes of the thyristors, and do not limit the direction of current flow in the thyristors. In addition, during a normal operation of the circuit, the low-voltage source line Vss is usually connected to a ground potential (i.e., is usually grounded), in order to fix the electric potential.
Still referring to FIG. 1, according to different directions of the current flow from the electrostatic-discharging terminal 3 at different electric potentials to the high-voltage source line Vdd and the low-voltage source line Vss during an ESD, four operating modes of the bidirectional thyristors can be defined. That is, the first thyristor 1 works in a negative-to-Vdd (ND) mode or a positive-to-Vdd (PD) mode, while the second thyristor 2 works in a positive-to-Vss (PS) mode or a negative-to-Vss (NS) mode.
FIG. 2 depicts a cross-sectional view of a conventional SCR ESD protection device. As shown in FIG. 2, the device includes a P-type substrate 100, an N-well 101 and a P-well 102 that are in the P-type substrate 100 and are adjacent, a first N+ type implanted region 201 and a first P+ type implanted region 202 located at the surface of the N-well 101, a second N+ type implanted region 204 and a second P+ type implanted region 205 at the surface the P-well 102, and an N+ type connection region 203 that extends across the surface of the N-well 101 and the P-well 102. The various implanted regions described above and the connection region 203 are isolated from each other by shallow trench isolation (STI) structures 109. The first N+ type implanted region 201 and the first P+ type implanted region 202 are connected with each other, to be used as the anode of a thyristor. The second N+ type implanted region 204 is used as the cathode of the thyristor. The second P+ type implanted region 205 is grounded. When being used in an ESD protection circuit as shown in FIG. 1, the second P+ type implanted region 205 can be connected to the low-voltage source line Vss. Although the N+ type connection region 203 is depicted as a region in FIG. 2, the N+ type connection region 203 is merely a surface layer formed via an implantation process that is limited to the surface of the thyristor, i.e., limited to the surface of the N-well 101 and the P-well 102.
FIG. 3 depicts an equivalent circuit diagram of a conventional SCR ESD protection device as shown in FIG. 2. Combing FIG. 3 with FIG. 2, the N-well 101, the P-well 102 and the second N+ type implanted region 204 form an NPN-type transistor T2. According to the difference in implantation concentration, a PN junction formed by the P-well 102 and the second N+ type implanted region 204 is an emitter. Similarly, the first P+ type implanted region 202, the N-well 101, and the P-well 102 form a PNP-type transistor T1. According to the difference in implantation concentration, a PN junction formed by the first P+ type implanted region 202 and the N-well 101 is an emitter.
Because adjacent regions having the same doping type can be considered as electrically connected regions, an equivalent circuit of the thyristor can be connected as follows. The emitter of the NPN-type transistor T2 is connected to the cathode of the thyristor. The base of the NPN-type transistor T2 is connected to the collector of the PNP transistor T1. The collector of the NPN-type transistor T2 is connected to the anode of the thyristor via an equivalent resistance Rnwell of the N-well 101. Meanwhile, the base of the PNP transistor T1 is connected to the collector of the NPN-type transistor T2. The emitter of the PNP transistor T1 is connected to the anode of the thyristor. The collector of the PNP transistor T1 is connected to the ground potential via an equivalent resistance Rpwell of the P-well 102. The NPN-type transistor T2 and the PNP-type transistor T1 form a typical thyristor structure. When a forward bias voltage is externally applied between the anode and the cathode and exceeds a trigger value, the bias voltage needs to form a reverse breakdown current between the N-well 101 and the P-well 102 in order to form a stable current in the thyristor without the need of additionally configuring a control electrode.
However, the performance of the existing SCR ESD protection device is still to be improved. The disclosed methods and structures are directed to solve one or more problems set forth above and other problems.